A ROM (Read Only Memory) is an array of ROM cells. A top view of a conventional array of ROM cells is shown in FIG. 1 and a cross section of an individual cell is shown in FIG. 2. A ROM array has some cells which are conductive and some cells which are not conductive. A ROM mask process allows selective implantation of the ROM code, so that some cells are conductive and some are not. The purpose of a mask ROM process is to enable some cells to be conductive and others to not be conductive. This conductivity selection is accomplished by selective implantation of ions, such as boron, into the channels of selected ROM cells.
Referring to FIGS. 1 and 2, the ROM array 10 is formed on a substrate 11 having a first dopant type. Illustratively, the substrate is P-type silicon with a doping concentration of 10.sup.15 /cm.sup.3. A plurality of parallel N.sup.+ type buried bit lines 12 are formed in the substrate 11. A plurality of polysilicon word lines 14 are formed orthogonal to the bit lines on the surface of the substrate 11. The ROM comprises a plurality of cells. One such cell 13 is delineated in FIG. 1 and shown in a cross-sectional view taken along line AA' in FIG. 2.
As shown in FIG. 2, the cell 13 comprises two parallel buried bit lines 12 which form source and drain regions for the cell. A channel 20 of length S is formed between the two bit lines in the cell 13. A gate oxide layer 21 is formed on top of the substrate 11. The oxide layer is thick at portions 22 which are located above the bit lines 12 and thin at portion 23 located over the channel 20. The thick portions 22 are approximately 350 Angstroms and the thin portions 23 are approximately 200 Angstroms. A polysilicon word line 24 is formed over the gate oxide layer 21. A photo resist layer 25 is formed and patterned on the polysilicon layer as a mask. Boron is implanted in cells for which the photoresist layer is removed and not implanted in cells which remain covered by the photo-resist. The implanted boron turn off the conducting state for the "off" cell (this programs the cell).
These conventional memory cells are programmed by the implantation of a ROM code via ROM code masking process. This type of programming is problematic for a number of reasons including 1) the alignment of the implanted code is difficult, 2) the voltage level of the junction breakdown is limited and 3) the resulting cells are unsuitable for high voltage operation.
It is an object of the present invention to provide a memory cell which is programmed by the presence or absence of a spacer short.
It is another object of the present invention to provide a memory cell which is self-aligned in programming.
It is still another object of the present invention to provide a memory cell which is suitable for higher voltage operation and lower junction leakage.
It is yet another object of the present invention to provide a memory cell having a junction breakdown voltage greater than 10 volts.